What if you could maximize the number of photonic test sites in a multi-project-wafer (MPW) run, where even an area as small as 10 mm² can cost tens of thousands of dollars? We pointed the autonomous design loop from our earlier posts at exactly that question, handed it a device library and a foundry rule deck, and let it run. It filled a fixed 8 x 3 mm die with 306 test structures, every one placed, routed, and DRC-clean, at 82% area occupancy, in a handful of free, local iterations that finished in minutes. The same layout by hand would take an engineer the better part of a day.
The loop filling the die. It first ramps replicates of the whole experiment to capacity, then plugs the leftover gaps with more real test structures until nothing more fits. Every frame is a live render of the actual layout.
This continues our series on agentic photonic design. The splitter post let an agent invent a Y-junction from a blank slate; the routing post had it wire a chip with zero rule violations. Here we ask whether an autonomous agent can take on the design-of-experiments and floor-planning of an MPW run: decide what to measure, turn each device into a measurable test structure, and tile as many as physically fit onto a fixed die.
A Design-of-Experiments (DoE) chip is a parameter sweep you can measure: instead of one nominal device you fabricate a ladder of variations and read the trend off the wafer. The loop starts from a library, and the point is that the library is yours. Each entry is either a PhotonForge parametric cell (a PCell, swept by argument) or a GDS file you hand it; the agent loads either, finds its optical ports, and wires it into a site.
Packing rectangles is easy. Packing measurable, manufacturable, probeable test structures is not. Each device has to become a self-contained site with its own optical and electrical access: a grating-coupler pair feeding an optical loopback, and, for active devices, bond pads for the electrical probe. On top of that, every site must keep the same orientation, so an automated wafer prober lands its fiber array and probe card identically at each one. That single rule forbids the packer from rotating sites to squeeze them tighter.
The work splits across two agents that never share a context window, only a file. A planner reads the library and designs the experiment: which parameter of each device to sweep, over what range, how many points, and which devices need electrical pads. It writes that plan to disk. A separate packer reads the plan and tiles the die. Handing the intent off as a plan file is what lets each agent stay focused, and lets you inspect or edit the experiment before a single structure is placed.
The planner designs the experiment and writes it to doe_plan.json. The packer reads it and runs a build-verify-score-journal loop, keeping a running journal so its reasoning survives across iterations. Everything here is free and local; no cloud simulations run.
The packer does not pack in one shot. It journals every move and adapts its strategy as the die fills. It begins by replicating the whole experiment, pass after pass, until one more full copy will not fit, which is how a real test chip samples process variation across the reticle. When the uniform tiling runs out of clean room, it switches tactics: find the largest empty rectangle that can still hold a device, fill it with more real structures, and repeat. It stops on its own when no remaining gap can hold even the smallest device in the library. The journal is what makes that two-phase behavior possible without a human watching: each entry records what changed, the gated score, and whether the step was kept.
An agent can only be trusted to pack a tape-out if it is never grading its own homework. So the bulk of the project was not the loop, it was the toolbox the loop calls, the same instruments a layout engineer reaches for, exposed as functions the agent can run in seconds:
Foundry DRC. The real SiEPIC KLayout rule deck, run as a subprocess: silicon and metal width and spacing, metal overlap, dicing boundary.
Geometric collision check. Boolean intersections on the routing layers return the exact overlap polygons, catching two sites touching, a route curling back on itself, or metal crossing a heater filament outside its contact window.
Connectivity (LVS-style). Every site's intended optical path is physically realized, with no dangling ports or unconnected nets.
Orientation gate. Confirms every placed site shares one pose, which is the wafer-prober rule turned into a pass/fail check.
Largest-empty-rectangle finder. Rasterizes the placed layout and returns the biggest packable gap left, which is how the void-fill phase knows where to go next and when to stop.
Live layout viewer. Renders the die at every step, so the agent can look at what it built and we can capture the animation above.
These roll up into a single gated figure of merit: maximize the number of placed structures, but score zero if any hard check fails. The agent cannot trade a violation for a higher count, and it always knows, in seconds, whether an idea is legal.
The run ends at 306 routed, clean structures and 82% occupancy. The experiment it actually built, counted off the final layout:
|
device |
source |
sweep |
sites |
|---|---|---|---|
|
straight |
PCell |
length 25 to 800 µm; core width 0.4 to 2.0 µm |
89 |
|
spiral |
PCell |
length 1 to 4 mm |
21 |
|
directional coupler |
PCell |
gap 0.18 to 0.36 µm; coupling length 5 to 20 µm |
58 |
|
crossing |
PCell |
intersection width 0.6 to 1.8 µm |
28 |
|
heater |
PCell |
length 50 to 300 µm; width 3 to 6 µm |
56 |
|
segmented-CPS modulator |
PCell |
length 300 to 1000 µm |
25 |
|
Y-branch |
GDS |
replicates |
29 |
|
total |
306 |
||
Tiling boxes is the easy part; PhotonForge already ships a bin-packing primitive (pack_layout, a skyline best-fit) the agent uses for the geometry. The hard part is that a chip can be perfectly DRC-clean and still worthless. A geometric rule deck checks widths and spacings, but not whether a probe pad lands where the fiber array must, or whether a site is rotated past where the prober can reach. Those are measurement errors, not polygon errors.
A layout that passes DRC is manufacturable. A layout that also respects fiber pitch, probe pitch, and a single prober orientation is measurable. The second is the harder bar, and it is the one that decides whether the wafer you paid for returns any data.
The entire run was autonomous and finished in minutes, against the hours of careful layout it replaces. The broader point is that with the right checks and harnesses in place, an AI agent can take over a previously tedious, manual task end to end. The engineer's attention moves to what actually matters, ensuring the chip is measurable and manufacturable, while the tiling, routing, and rule-checking are handled underneath.
The agent was also honest about its limit. We asked for 95% occupancy; it reported the real ceiling at about 82% and explained why: with one fixed orientation, each loopback site is mostly air, since a grating-coupler pair at the 127 µm fiber pitch reserves far more area than the device it measures. The next gains come from denser test structures, letting several devices share one grating-coupler pair or chaining devices in a single loopback to multiply the experiments per die.
Try it yourself. Install PhotonForge and the SiEPIC PDK, then point your agent (Claude Code, Cursor, or VS Code) at the doe_packing branch of autophotonicdesign to run the baseline and design your own experiments.