Photonic chips are packed with active elements such as heaters, modulators, and detectors, and every one of them needs a metal wire from its contact pad to a bondpad at the die edge. Drawing those wires is the unglamorous plumbing step at the end of layout, but it is also where projects stall: dozens of nets have to reach their targets without crossing each other, without cutting over a heater, and without overlapping a pad. Below is a finished photonic chip, with every copper-colored trace the result of that plumbing.
This post is a companion to Tom's recent Photonic Device Auto-Design Agent, which showed an AI agent iterating on a single photonic device. We were inspired by that demo and asked: can the same loop handle a full-chip layout problem? Specifically, can an agent take over DC routing?
Autoresearch, popularized recently by Andrej Karpathy, is the idea that you give an AI agent a goal, a code editor, and a way to run experiments, then let it iterate. Hypothesize, code, run, analyze, repeat.
The pattern fits photonic chip design well. Any problem where an agent can propose a design, evaluate it against a figure of merit, and learn from the result is a good candidate. We tested it on electrical DC routing, the step where every active element on a photonic chip needs a metal trace connecting it to a bondpad at the die edge. On a modern chip that means dozens of traces that must reach their targets without touching each other, without passing over a heater, and without overlapping a pad.
The Auto-Design loop. A human writes the goal once. The agent edits a routing script, the layout tool builds it, a design-rule checker returns pass or fail counts, and a journal remembers every attempt.
We pointed the agent at a projector chip with thirty-two metal contact points that needed to reach thirty-two bondpads. The starting script was what any engineer would type first: call the built-in point-to-point router once per pin, and hope.
The naive starting point. Every net routes selfishly and hits everything else.
That first attempt produced 192 violations. Thirty of the routes cut straight through a heater. A hundred and sixty-two pairs of routes crossed each other.
The agent went to work. It switched to a grid-based planner so nets could share the chip politely. It taught the planner about heaters so routes stopped cutting through them. It adjusted how pins were paired with bondpads, widened the bondpad row, and eventually diagnosed a last-mile edge case where a single contact sat awkwardly close to one heater. One clean constraint later, every net reached its pad.
The agent's final layout. All thirty-two nets routed, zero design-rule violations.
The agent ran 27 iterations end to end, each one building a fresh layout, routing, and checking every design rule.
Total wall-clock: 2 minutes 25 seconds.
That includes every failed attempt, every rebuild, and the final polish. A human engineer laying this out by hand, pairing pins to pads, sketching the bundles, and chasing the last few DRC violations, typically needs two to three hours to get to the same clean result.
The infrastructure behind this loop is not trivial. Making it work took a real photonic layout engine (PhotonForge), a library of routing algorithms such as Manhattan, grid BFS, A*, bundle routing, and rip-up-and-reroute, and a suite of verification tools that turn the chip into a dense grid, detect route-to-route collisions, flag heater crossings, and report everything as a single loss number the agent can optimize against. Each of those pieces is its own small project.
What made this experiment interesting is that the agent could pick up those tools and try ideas faster than any of us could. It rediscovered grid planning, obstacle inflation, pin-to-pad assignment, and bundle shifting on its own, ran 27 full-chip rebuilds in the time it takes to make coffee, and diagnosed a single-contact edge case by reading its own DRC report. No human suggested any of it.
Now imagine this at scale. Many chip designs in parallel, each with its own pin lists and constraints. The agent never tires, never forgets a failed iteration, and context-switches between chips effortlessly. The future of photonic layout looks less like an engineer dragging metal for an afternoon, and more like writing a one-page spec and handing it to an agent that returns a foundry-ready design by the time you come back from lunch.
The creativity does not disappear. It moves up the stack.
We are just getting started.
Ready to experience agentic photonic design automation with PhotonForge?
Bring your own chip, point an agent at it, and watch the routing solve itself.