This case study showcases powerful layout and routing capabilities in PhotonForge through the design of a two-qubit quantum processor chip. We demonstrate full-chip layout implementation with comprehensive electrical and optical routing. 

Overview

Quantum photonic integrated circuits (QPICs) are poised to transform scalable quantum computing and secure communications. One of the foundational elements in these systems is the ability to design and simulate quantum photonic chips with high precision, especially for devices that perform quantum interference, entanglement, and state manipulation.

In this case study, we demonstrate how PhotonForge—an advanced photonic simulation platform built on Tidy3D—enables accurate and efficient modeling of a quantum photonic chip using layout-driven design and 3D electromagnetic simulation.

Explore the complete example: Quantum Photonic Chip Simulation in PhotonForge Documentation

Challenge

Designing and simulating quantum photonic circuits involves unique complexities:

1. Complex topologies with high precision
   
   Quantum circuits require complex waveguide networks consisting of interferometers, beam splitters, couplers, and phase shifters. The performance of these components is highly sensitive to geometry and fabrication tolerances. Even nanometer-scale variations can affect the fidelity of quantum operations.

2. Lack of integrated design-to-simulation workflow
   
   Traditional photonics design tools often require exporting GDS files, generating separate mesh models, and manually setting up 3D simulations. This fragmented workflow increases simulation time and can lead to errors.

3. Simulation performance and scalability
   
   Full 3D FDTD simulations of photonic chips are computationally expensive and time-consuming, especially for dense layouts with multiple ports and long propagation paths. This makes it difficult to iterate quickly and explore design variations.

Objective

This study aims to simulate a quantum photonic chip that demonstrates the routing and interference of a single optical input across a network of beam splitters and waveguides, resulting in light distribution across multiple output ports.

Specifically, we aim to:

• Simulate the entire chip in 3D, including mode excitation, field propagation, and power splitting.

• Visualize the electromagnetic fields in the chip to study modal evolution and interference patterns.

• Measure the power at each output port to confirm expected performance (e.g., balanced splitting, constructive/destructive interference).

• Evaluate PhotonForge’s workflow, particularly its layout-driven simulation interface, automatic meshing, and cloud-based FDTD execution.

The chip layout should represent photonic platforms fabricated in silicon nitride or SOI processes, operating at telecom wavelengths (~1.55 μm).

Simulation Workflow with PhotonForge

PhotonForge streamlines the simulation pipeline by enabling the user to go from layout to 3D FDTD simulation in a few steps.

1. Layout design

The photonic chip is defined directly in the PhotonForge layout editor using Python scripting or GUI tools. The layout contains:

• • Individual components: A waveguide crossing and spiral used divede and recombine light across different paths can be imported from an in-built parametric library,

     

     

    a 2x2 MMI with multiple arms designed for path-length matching and interference from the LNOI400 PKD, and a waveguide termination with an optimized bending shape to avoid extraneous reflections in unused ports.
    

    

  • Phase-controlled MZI with phase shift control are key building blocks in the quantum processor. It comprises from the optical ports, electrical terminals and customized model.

  • Full devices: We split the full devices into sub-components that can be re-used and combined into the full device layouts. Each is implemented as a parametric component to enable advanced analyses later as needed.
    

  • Fianl layout: Combine each devices and route all terminals to side pads to build the final layout.
    

The layout mimics real experimental chips used in linear optical quantum computing, where the coherent evolution of photons through beam splitter arrays results in probabilistic outputs determined by quantum interference.

2. Automatic 3D Mesh Generation

PhotonForge constructs the 3D simulation model automatically using the layout and layer stack, including vertical thicknesses and lateral features. The meshing algorithm ensures satisfactory resolution at material interfaces and waveguide boundaries.

3. FDTD Simulation with Tidy3D

Typically, in materials like SiN or Thin-film Lithium Niobate (TFLN), individual components have a larger footprint than Si photonics devices since the refractive index is closer to 2.  With the generation of Tidy3D models directly from PhotonForge and the ability to run GPU-accelerated simulations with a single s-matrix function call, it is possible to speed up simulation time by >100 times dramatically.

Conclusion

This case study illustrates how PhotonForge can simulate a full quantum photonic chip with minimal manual setup, high physical fidelity, and rapid turnaround. PhotonForge enabled the rapid design and accurate simulation of a quantum photonic chip using layout-driven 3D FDTD simulation. The study showcases how photonic engineers and quantum researchers can:

Quickly move from layout to simulation without manual CAD or meshing.

Gain physical insight into modal behavior, power distribution, and interference.

Iterate on design with cloud-based FDTD, running full 3D simulations in minutes.

Key Benefits

Explore the example

Quantum Photonic Chip Simulation in PhotonForge Documentation