Design for manufacturing
We spend months designing and optimizing a photonic circuit, and manufacturability usually comes last. For building a real product it decides everything. Here is how I went from a finished cascaded MZI filter to full component-to-circuit yield statistics in an afternoon, and why doing yield analysis is more than brute forcing through FDTD simulations.
A photonic engineer at Flexcompute · variation-aware yield, start to finish.
Every die on this wafer got the same mask. As I walk from die to die, the filter passband moves, and some dies fall outside the spec window. This is the difference between the circuit I designed and the circuits the fab actually makes.
Silicon photonics devices are sensitive to fabrication variations. On this filter, one nanometer of silicon thickness moves the passband by 1.4 nm, and the channel spacing is only 10 nm. Whether a product works is a combination of good design and one that is robust against fabrication variations. Often times we spend a lot of time designing a perfect response and postpone the question of how manufacturing impacts the design. This matters not just when you are building at scale, but when you are building large circuits with cascaded elements or trying to achieve sensitive interference effects.
Deriving circuit statistics from device statistics has been a known goal for years. Bogaerts and Chrostowski name it directly in their 2018 review[1]: the circuit performance statistics need to be derived from the functional device statistics, combined with location-dependent, correlation-aware methods. The pieces are individually hard. Full-fidelity device simulation is expensive. Composing many devices into a layout-aware circuit simulation is its own tooling problem. Variation is position-dependent and correlated across a wafer, not random per device. And the compact models have to stay physical, meaning passive, causal, and phase-correct, as you perturb them.
Silicon thickness across three representative wafers, one per lot. Variation is structured, not noise: whole wafers shift together, and there is a smooth trend across each one.
The obvious approach is to Monte-Carlo the whole circuit and re-simulate every device on every draw. With five couplers and thousands of chips, that is tens of thousands of FDTD runs. It is hard to scale and would take a very long time, so it does not fit into a design loop.
The next reflex is to fit a surrogate model and skip the repeated simulation. That helps, but a black-box fit over raw S-parameters, whether a Gaussian process or a neural network, still needs a lot of samples, and it can quietly break passivity. I hit exactly this earlier in the project: small per-device errors that do not conserve energy accumulate through a five-coupler cascade into several dB of loss that is not real. Phase and delay are just as unforgiving. A filter is an interference device, so if the surrogate does not match the phase and group delay of each arm and coupler, the passband lands in the wrong place even when the magnitudes look fine.
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~50,000 FDTD runs to brute-force the Monte Carlo |
44 FDTD runs, once, for the whole study |
~1.4 s per chip, no FDTD in the loop |
600 virtual chips in 14 minutes |
The trick is to stop fitting raw S-parameters and fit the physical knobs instead: the coupling angle, the common phase, and a small amplitude term for each building block. Built this way the model is unitary and delay-correct by construction, and it stays continuous in thickness, linewidth, and wavelength. This is where the AI matters. It now has access to all the analytical compact models that human designers built and verified over the years, so instead of throwing samples at a black box it picks the right parametrization and finds a sample-efficient fit far more easily. PhotonForge then composes these models in a hierarchy to build the full circuit, which in the past would have taken a lot of careful, custom effort.
To trust a surrogate you have to test it on points it never saw during fitting. I trained each coupler on a small design-of-experiments over the process corners, then held out separate FDTD runs and checked the model landed on them, including the group delay. That is the difference between a curve that memorized its training points and a model that actually interpolates.
One coupler's surrogate. FDTD points (dots) sit on the surrogate curves (lines) across the band. The held-out corners, which were never used in the fit, match to within 0.002 in coupling ratio and 10 mrad in phase, and the group delay overlays the FDTD to a fraction of a femtosecond.
A surrogate that conserves energy and matches phase and delay is what lets you cascade five couplers and four delay arms without inventing loss or drifting the passband.
With every device modeled, I lay variation down the way it actually happens. A lot offset, a wafer offset, a slow systematic trend across each wafer, and a spatially correlated random field on top, with thickness correlating over centimeters and linewidth over millimeters. Every component of every die then reads the map at its own position, so neighbors match and distant devices drift apart. That correlation is exactly what a corner analysis throws away.
Left: thickness and linewidth maps for one wafer, with the fixed set of measured die sites. Right: the same wafer populated with the filter die, the object the campaign scans.
An honest caveat: I do not have real wafer-scale thickness and linewidth maps for this process, so I used a physically reasonable simulated wafer. If you are serious about production, this is the one input you should not assume. Ask your foundry for their wafer maps, or measure your own with profilometry, ellipsometry, and electrical or optical test structures. Even so, a spatially correlated virtual wafer is far more informative than a nominal curve and a corner sweep, because it captures the device-to-device mismatch and position dependence that interferometric circuits are sensitive to.
I then ran 600 virtual chips, three lots of five wafers with forty dies each, in about fourteen minutes at roughly a second and a half per chip, with no FDTD in the loop. The output reads like a measurement report rather than a simulation.
Passband shift per wafer, grouped by lot, against the ±5 nm spec. You can see the lot signatures: one lot runs thin and drops toward failure while another sits high.
The verdict is a 64% yield against a ±5 nm spec, and the variation splits into 3.5 nm lot-to-lot, 2.8 nm wafer-to-wafer, and 3.0 nm within a wafer. With that in hand you can start making design decisions to make the circuit more robust: making each directional coupler longer with wider gaps, turning the straight segments into multimode or slab waveguides so they are less sensitive to thickness variation, or adding a thermal heater to tune the offset out.
All 600 chips as one distribution with the yield number, and the variance broken down by lot, wafer, and within-wafer. This is a yield report for a chip that does not exist yet.
With a bit of AI intuition this approach generalizes. The same three steps have held up across different devices and different foundry processes in our internal work, from a ring-based WDM filter to a foundry coupler to an MMI. What changes is the PDK and the metric, not the method. The turn here is that a tedious, custom workflow became an automated, agentic one. It is packaged as a yield skill and plugin driven through the flexagent interface, so the whole analysis is a short conversation rather than a codebase to maintain.
With all these integrated simulation tools linked together, component simulation through to foundry PDKs, layout, schematic, and circuit simulation, that an agent can natively drive, and with the human-built notebooks and models the AI can reference when building surrogates, this kind of analysis becomes very accessible. Getting real measurement data for the models will improve the prediction, but even without it you get something that lets you walk into your fab with a bit more confidence that your design will work the first time.
The distribution a corner analysis cannot show: sampled chip spectra sweeping across the spec window, colored by how far each one shifted.
Cascaded MZI CWDM filter on the SiEPIC open PDK. Device surrogates from Tidy3D FDTD and mode solves; circuit statistics and virtual wafers in PhotonForge. Variability parameters are illustrative and should be calibrated against foundry or measured wafer data for production use.
[1] W. Bogaerts and L. Chrostowski, "Silicon Photonics Circuit Design: Methods, Tools and Challenges," Laser & Photonics Reviews 12, 1700237 (2018). doi:10.1002/lpor.201700237.