Inverse design is a powerful tool, but enabling great designs requires careful thought about a number of things: how the geometry is parameterized, how the figure of merit is defined, how the optimizer routine is structured, and whether the result still works once it leaves the simulator and reaches a fab line.
"What can Tidy3D's inverse design do? Which features are supported?" We get these questions a lot. We could answer by listing features one at a time, but it is more concrete, and more interesting, to show them through a single example from photonic integrated circuit design: a compact, broadband, 4-channel mode demultiplexer.
The full design story: the structure evolving from a grayscale start to a fabrication-robust binary device, the resulting fields, and the per-channel spectra.
The complete run, start to finish: the design evolving from its grayscale initialization into a fabrication-robust binary device, the field distributions it produces, and the resulting per-channel spectra.
The example is inspired by the topology-optimized device of Shen et al. (Photonics Research 12, 2891, 2024). Four single-mode input waveguides feed a 6 × 6 µm freeform design region on a 220 nm silicon-on-insulator platform. The optimizer can place silicon anywhere in that region, so that each input is routed and mode-converted into a distinct mode of a shared 1.6 µm multimode bus:
- I1: TM0 → TM1
- I2: TM0 → TM0
- I3: TE0 → TE1
- I4: TE0 → TE0
That is two TE channels and two TM channels combined onto one bus, over the full 1500–1600 nm band (Figure 1). We parameterize the design region as 90,000 permittivity pixels on a 20 nm grid.
Field distribution at 1550 nm for each of the four inputs, each converting into its target bus mode.
Figure 1. Field distribution at 1550 nm for each input. Every single-mode input is routed across the design region and emerges in its target bus mode: TM0→TM1, TM0→TM0, TE0→TE1, TE0→TE0.*
This is a multi-frequency, multi-port, and multi-mode optimization, driven by a fully customized objective function:
Multi-port. Each of the four inputs is its own excitation, so every gradient step is a batch of simulations launched and run in parallel on the cloud.
Multi-mode. A polarization-sorted ModeMonitor on the bus decomposes the output field onto the guided modes by overlap integral, so TE0/TE1 and TM0/TM1 come out cleanly separated. That separation is the whole point here, because the objective has to know which mode the light actually ended up in.
Multi-frequency. The objective is evaluated at 11 wavelengths across the 100 nm band. Because frequency-domain monitors accumulate during a single time-domain run, this broadband objective adds essentially no cost over a single-wavelength one.
The objective is not a simple average of the channel efficiencies. Instead we use their softmin, a smooth approximation to the single worst-performing one. We avoid averaging because it lets the optimizer do well on the easy channels and ignore a weak one, since the mean still looks acceptable. The softmin keeps the gradient focused on whichever channel is currently worst, so the optimization works to bring up the weakest case.
The objective also carries an erosion/dilation penalty. This is the first of two places erosion and dilation show up in this project, and the two are easy to confuse, so it is worth being exact about each. The penalty is purely geometric: every step it erodes and dilates the current pattern and measures how much the shape changes. Narrow tips and small gaps or holes are penalized. It is computed straight from the design's permittivity distribution, with no simulation involved, and its only job is to keep the layout fabricable by enforcing a minimum feature size. Figure 2 shows the effect of this penalty: the bright spots, marking the regions with the highest penalty, fall on the thinnest features and narrowest gaps, exactly the structures that would struggle to survive fabrication.
Map of where the erosion/dilation penalty is active across the design region.
Figure 2. The erosion/dilation penalty distribution. The heatmap is the per-pixel difference between a morphological closing and opening of the design. The design outline is in cyan. High penalty value concentrates on small islands and narrow tips, the features most at risk in fabrication.
The optimization strategy is also fully under our control. We ran the first 60 iterations in grayscale, letting the optimizer find good routing and conversion physics before imposing any manufacturing constraints. From iteration 60 on, we ramped a binarization projection (β from 1 to 100) to drive the design toward a clean, foundry-ready binary layout. At the same point we switched on the etch variants. This is the second place erosion and dilation appear, and it is a different mechanism from the penalty above: instead of simulating one device per channel, we simulate three, a nominal one, a uniformly eroded copy (over-etch), and a uniformly dilated copy (under-etch), at a ±8 nm edge bias in each direction. All 12 channel-and-etch combinations feed into the softmin. Figure 3 shows the three states at a single region, where the dilated, nominal, and eroded boundaries trace out the ±8 nm variation.
Zoom showing the under-, nominal-, and over-etched boundaries of a feature.
Figure 3. The three etch states at a representative feature (zoom). Silicon is gray, cladding is white; the blue, black, and red contours are the under-etched (dilated), nominal, and over-etched (eroded) boundaries. The gap between the blue and red contours is the ±8 nm fabrication window the optimizer designs against.
The contrast between the two is the key point. The penalty looks only at the geometry and asks whether a feature can be fabricated, and it adds no simulations. The etch variants run the physics and ask whether the device still works once it has been fabricated slightly wrong. Each variant is a full FDTD simulation, which is why the forward pass triples in this phase, from 4 simulations per step to 12. One keeps the layout clean; the other keeps the response tolerant. The robustness is built into the gradient itself.
It's important to note that none of these techniques are technically required. These techniques are choices we made to push toward a fabrication-tolerant device. They are not prerequisites for all inverse design.
The figure of merit climbs through the grayscale phase. It drops noticeably when binarization and the etch variants switch on, which is expected, because the design now has to be both binary and fabrication tolerant, and then recovers. At 1550 nm, it shows 0.55–0.72 dB insertion loss and −21 to −30 dB worst-case crosstalk across the four channels (Figure 4). Across the full ±8 nm etch band the insertion-loss and crosstalk curves barely move: the under-, nominal-, and over-etched traces sit almost on top of one another, which is the robustness we optimized for (Figure 5).
Per-channel target-mode transmission and crosstalk across the band.
Figure 4. Per-channel spectra across 1500–1600 nm: target-mode transmission and crosstalk for each of the four channels.
Insertion loss across the etch window.
Figure 5. Insertion loss across the ±8 nm etch window. The under-, nominal-, and over-etched curves nearly overlap, confirming the design's tolerance to fabrication error.
This complex optimization only comes to a few hundred lines of Python on Tidy3D's autograd API. The full 150-iteration run executed on the cloud for roughly a hundred FlexCredits.
This example really showcases the features and flexibility of inverse design in Tidy3D, which can meet the stringent requirements of state-of-the-art designs and research. However, it only reflects one possible workflow: a ModeSource in, a density-based design region defined as a CustomMedium, and ModeMonitor's out. The same differentiable machinery handles any source type, shape or parameterized-geometry optimization, and objectives built from other data, such as raw field profiles or near-to-far-field projection. We tried to use as many features as possible in this example, but many other useful features went unused. For the full list, see the Tidy3D autograd plugin reference.